WORKSHOP
AI Chips with Open Source and AI: A Practical Path to Production
Date: 07th October 2026 Time: 03:30 to 6:00 PM
Venue: Workshop Room 1, NIMHANS Convention Centre, Bangalore
FEES:
• Rs.299 for Leaders Pass holders
• Rs.2009 for Professionals Pass holders
• Rs.2249 for Knowledge Pass holders
• Rs.2699 for Community++ or Student Pass holders
• Rs.2999 for all others
(Limited seats available)
Show, hands-on, that a working AI-capable ASIC can be taken from RTL to a fabrication-ready GDSII using only open-source tools and open PDKs – no proprietary EDA licences. In two hours, attendees walk the complete path to production: designing and hardening a small neural-network / accelerator block with the LibreLane (OpenLane) + OpenROAD flow on the SkyWater SKY130 open PDK, verifying it (DRC/LVS clean), and then mapping that same flow to India’s real, government-backed silicon route – the SCL Mohali 180nm node accessed for free through the Chips-to-Startup (C2S) programme, the ChipIN Centre (C-DAC Bengaluru) MPW shuttles, and the Design Linked Incentive (DLI) scheme. The goal is to leave every participant convinced that open-source silicon + AI is not a lab curiosity but a practical, low-cost, sovereign route to real chips.
Raja Gopal Hari Vijay
Member Leadership Staff, Zoho Corporation
- Embedded, hardware, VLSI and FPGA developers; students and faculty in ECE/EEE; AI/ML engineers curious about custom silicon and edge-AI accelerators; startup founders and R&D teams evaluating a low-cost path to a first tapeout; and open-source enthusiasts who want to understand how ASICs and SoCs are actually built. It is aimed at people comfortable with basic digital logic and a Linux terminal - deep prior chip-design experience is NOT required.
- 2-hour hands-on workshop. Follow-along using the open repo github.com/rajaghv-dev/open-silicon-lab (11 open-source SKY130 designs, all 0-DRC verified).
- Part 1 (0:00-0:20) - Why open silicon + AI now: the RTL-to-GDS problem, cost of proprietary EDA, and how open PDKs (SKY130) + open tools changed the game.
- Part 2 (0:20-0:40) - The open-source toolchain: Yosys (synthesis), LibreLane/OpenLane + OpenROAD (place-and-route, RTL2GDS), Magic + KLayout + Netgen (DRC/LVS signoff). One-command environment setup.
- Part 3 (0:40-1:15) - Live build 1: harden a simple block (serial multiplier -> Wishbone counter) end-to-end; read flow.log, floorplan, timing closure, and inspect the GDS.
- Part 4 (1:15-1:45) - Live build 2, the AI chip: harden a small neural-network accelerator (binarized / fixed-point MNIST classifier, scaling toward a float16 CNN inference core) and integrate it as a Caravel user project - showing an actual AI ASIC block.
- Part 5 (1:45-2:00) - Path to production via support programs: taking your GDS to real silicon on SCL Mohali 180nm for free through the C2S programme and ChipIN Centre (C-DAC) MPW shuttles, plus the DLI scheme for startups - what to submit, timelines, and how to get your institution registered. Q&A.
Benefits/Takeaways of this workshop for the attendees (What will attendees do after attending the workshop which they were not able to do before attending this)
Attendees are able to run a complete open-source RTL-to-GDSII flow themselves and with a clear, actionable route to fabricating a real chip. Specifically they will: (1) set up and run LibreLane/OpenLane + OpenROAD on the SKY130 open PDK; (2) take a design – including a small AI/neural-network accelerator – from RTL to a DRC/LVS-clean GDSII; (3) understand SoC integration via the Caravel harness; and (4) know exactly how to reach production for free through India’s government schemes (C2S programme, ChipIN Centre / C-DAC MPW shuttles at SCL Mohali 180nm, and the DLI scheme). They also get a ready-to-use, fully worked reference repo (open-silicon-lab) with 11 verified designs to keep learning from – proving ASICs/SoCs can be built openly, cheaply, and sovereignly.
A laptop (8GB+ RAM recommended) with Linux, macOS, or Windows-with-WSL2, and Docker installed (setup instructions shared before the session). Basic familiarity with digital logic (gates, flip-flops, RTL/Verilog) and comfort using a command-line terminal and Git. No proprietary EDA licences and no prior tapeout experience needed – all tools and PDKs used are free and open source. Optionally, clone github.com/rajaghv-dev/open-silicon-lab in advance to follow along.
About Speakers
Raja Gopal is an AI Systems Architect and technical leader building cost-efficient, low-power AI platforms across data center and on-device, spanning FPGA and SoC systems, model orchestration on hardware (NPU/iGPU/CPU), and enterprise-scale deployment. He lead a 20+ member multidisciplinary team and own outcomes end-to-end: system-level bottleneck resolution and enterprise methodology.
At Zoho (since 2018), he architects the full stack — from hardware acceleration to model orchestration on hardware, operating systems, and UX. My work spans: adapting and integrating AMD (Xilinx) U30, MA35D, and U55C accelerator cards into Zoho’s data center for cloud video transcoding and AI workloads (saving ~$4M from TCO); sub-precision (low-bit) AI inference for image and video understanding; a hierarchy of models with a context builder that dynamically maps workloads across NPU, iGPU, and CPU; CPU–FPGA co-design (via High-Level Synthesis) for image compression and video understanding on x86 laptop platforms; workload-optimized Linux OS distributions (incl. Surya OS) across x86 laptop and Android mobile; and natively integrated AI agents with full observability.
With 16+ years prior in chip design and verification at Intel, Texas Instruments, and Motorola (SPS), he contributed to SoCs and server chips. His work is backed by nine global publications across formal property verification, EDA, video AI, low-power AI chip design, and RISC-V in medical AI