AI Systems Architect and technical leader building cost-efficient, low-power AI platforms across data center and on-device, spanning FPGA and SoC systems, model orchestration on hardware (NPU/iGPU/CPU), and enterprise-scale deployment. I lead a 20+ member multidisciplinary team and own outcomes end-to-end: system-level bottleneck resolution and enterprise methodology.

At Zoho (since 2018), I architect the full stack — from hardware acceleration to model orchestration on hardware, operating systems, and UX. My work spans: adapting and integrating AMD (Xilinx) U30, MA35D, and U55C accelerator cards into Zoho’s data center for cloud video transcoding and AI workloads (saving ~$4M from TCO); sub-precision (low-bit) AI inference for image and video understanding; a hierarchy of models with a context builder that dynamically maps workloads across NPU, iGPU, and CPU; CPU–FPGA co-design (via High-Level Synthesis) for image compression and video understanding on x86 laptop platforms; workload-optimized Linux OS distributions (incl. Surya OS) across x86 laptop and Android mobile; and natively integrated AI agents with full observability. I reduce Total Cost of Ownership using energy-efficient PCIe accelerators and FPGAs.

With 16+ years prior in chip design and verification at Intel, Texas Instruments, and Motorola (SPS), I contributed to SoCs and server chips. My work is backed by nine global publications across formal property verification, EDA, video AI, low-power AI chip design, and RISC-V in medical AI